Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). SOI technology possesses many advantages over bulk silicon technology such as reduction of parasitic capacitance, excellent sub-threshold slope, elimination of latch up and resistance to radiation. Hence it is preferred for high speed, high -temperature and low power microelectronic devices. An SOI microchip processing speed is often 30% faster than today's complementary metal-oxide semiconductor (CMOS)-based chips and power consumption is reduced 80%, which makes them suitable for mobile devices.
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S. Modani; R. Sharma; P. S. Yahparveen_singhal@yahoo.com); S. Garg, "SOI Wafer Fabrication techniques: SIMOX and Smart CutTM", Journal of Ultra Scientist of Physical Sciences, Volume 20, Issue 1, Page Number 75-80, 2018Copy the following to cite this URL:
S. Modani; R. Sharma; P. S. Yahparveen_singhal@yahoo.com); S. Garg, "SOI Wafer Fabrication techniques: SIMOX and Smart CutTM", Journal of Ultra Scientist of Physical Sciences, Volume 20, Issue 1, Page Number 75-80, 2018Available from: http://www.ultraphysicalsciences.org/paper/1362/