SOI Wafer Fabrication techniques: SIMOX and Smart CutTM

Author & Affiliation:
S.G. Modani
Govt. Engg. College,.Ajmer (INDIA)
Rajeev Sharma (monrajanp@rediffmail.com)
Asstt., Prof. ECE, Dept., Vaish College, of Engg. Rohtak (INDIA)
Parveen Singhal yahparveen_singhal@yahoo.com)
Student M.E., Vaish College, of Engg. Rohtak (INDIA)
Shrutkirti Garg (shrutu_garg2000@yahoo.co.in
Student M.E., Vaish College, of Engg. Rohtak (INDIA)
Keyword:
Fabrication techniques:, SIMOX , Smart CutTM
Issue Date:
April 2008
Abstract:

Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). SOI technology possesses many advantages over bulk silicon technology such as reduction of parasitic capacitance, excellent sub-threshold slope, elimination of latch up and resistance to radiation. Hence it is preferred for high speed, high -temperature and low power microelectronic devices. An SOI microchip processing speed is often 30% faster than today's complementary metal-oxide semiconductor (CMOS)-based chips and power consumption is reduced 80%, which makes them suitable for mobile devices.

Pages:
75-80
ISSN:
2319-8052 (Online) - 2231-3478 (Print)
Source:
DOI:
jusps-B
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Copy the following to cite this article:

S. Modani; R. Sharma; P. S. Yahparveen_singhal@yahoo.com); S. Garg, "SOI Wafer Fabrication techniques: SIMOX and Smart CutTM", Journal of Ultra Scientist of Physical Sciences, Volume 20, Issue 1, Page Number 75-80, 2018

Copy the following to cite this URL:

S. Modani; R. Sharma; P. S. Yahparveen_singhal@yahoo.com); S. Garg, "SOI Wafer Fabrication techniques: SIMOX and Smart CutTM", Journal of Ultra Scientist of Physical Sciences, Volume 20, Issue 1, Page Number 75-80, 2018

Available from: http://www.ultraphysicalsciences.org/paper/1362/

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